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Design of Efficient Reversible Multiplier
Reversible logic is emerging computing paradigm with applications in Ultra-low power Nano computing, quantum computing, Low power CMOS design, Optical Information Processing, Bioinformatics etc. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct NxN reversible multiplier circuit.