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Low Delay Based Full Adder/Subtractor by MIG and COG Reversible Logic Gate
Reversible logic gates are implemented over a high scale in the future technologies. Reversible logic is seen as a demanding field with variegated applications like CMOS designs consuming less power. This paper proposed design of a full Adder/Subtractor circuitry with the help of fault tolerant based Reversible logic gates. In the given paper, a full adder/subtractor is proposed with help of MIG (Modified Islam Gate) & COG (Controlled Operation Gate) reversible logic gate comprised of pipelining. As observed from the outcome session, it is evident that delay will be minimized by around 61% by making use of COG & MIG Reversible logic gates contrasting Feynman Double Gate based Full Adder/Subtractor.
تاخیر کم مبتنی بر adder / Subtractor کامل توسط MIG و دروازه منطقی Reversible Reversible
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