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A Compact Quantum Cost-Efficient Design of a Reversible Binary Counter

One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as the number of devices integrated on a single chip increases progressively. In order to overcome the difficulties of high power consumption of a single chip, it is necessary to introduce reversible logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The potential applications of reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics and many more. Counter circuit stores the number of times of occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement in terms of garbage output compared to existing best known circuits.

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