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An Order Sampling Processing-in-Memory Architecture for Approximate Graph Pattern Mining

There have been increasing interests in graph pattern mining due to the booming of data volume in various domains. Conventional graph mining implementations which calculate the exact count of patterns usually suffer from huge amounts of intermediate data and low performance on large-scale graphs. With the observation that the exact pattern counts are not required in many real-world graph pattern mining problems, previous works (e.g., ASAP) proposed an approximate graph pattern mining algorithm and improved the performance of graph pattern mining by up to two orders of magnitudes. The crucial sampling operation in the ASAP algorithm exposes high parallelism and complex edge searching. Moreover, the performance of ASAP is closely related the sampling order. However, previous works failed to tackle these problems in the design. Thus, we propose a novel Processing-in-Memory (PIM) architecture for parallel approximate graph pattern mining problems. We introduce dictionaries on the logic layer of PIM devices for edge indexing. We also explore the design space of sampling orders and give the optimal sampling strategy. The comprehensive experimental results show that, our design achieves up to 97 times performance improvement against ASAP system.

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